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Cadence applies artificial intelligence (AI) and big data technology to the semiconductor design verification platform, and enhances advance system-on-chip (SoC) design error analysis.

Cadence recently launched an AI-based semiconductor verification platform, ‘Verisium'. Verisium can detect various errors such as bugs that cause semiconductor design problems with machine learning (ML) technology, and solve the issues quickly.

The release date for for semiconductor products is increasingly delayed as SoC designs become more complex. The delays is not only the development time but also the input of human resources such as engineers are increasing as the number of processes to identify design errors increases, which leads to an increase in production costs.

Cadence AI verification platform can maximize semiconductor design verification efficiency by utilizing ML models. It can predict test result in advance after completing semiconductor design, and automate verification repeatedly. By comparing semiconductor design assets (IP) or SoC source codes, it also provides an algorithm to accurately detect potential errors. This will compare design test pass and fail results simultaneously.

Cadence introduced 'I Special', which applied AI and ML technology to semiconductor design automation (EDA) tools in 2020. The semiconductor chip development cycle can be accelerated by dramatically reducing the semiconductor design process, AI technology has been expanded and applied not only to design but also to verification with this Verisium platform.

Cadence stated that, “In order to apply AI and big data to the EDA business, new technologies are required to optimize multiple execution engines. An era of AI-based verification has started with the launch of this platform, and users will be able to significantly improve verification productivity and efficiency.”

By Staff Reporter Dong-joon Kwon