Silicon Mitus launched a power management integrated circuit (PMIC) for LPDDR5 (low-power DRAM memory) on the 12th.
LPDDR5 is the next-generation low-power memory of LPDDR4. It is used in portable devices such as laptops, tablets, and smartphones. LPDDR5 is capable of adjusting the operating speed according to usage to reduce power consumption, and it minimizes power consumption during standby state and improves processing speed.
The PMIC for LPDDR5 converts, distributes, and controls the power that goes into LPDDR5. Silicon Mitus’ 'SM582x series' can adjust voltage and operating speed while running. Appropriate voltage is supplied in real time depending on the operating state.
Silicon Mitus PMIC’s lowest output voltage is 0.3V, which is a lower voltage compared to the existing 0.4V, and minimizes power usage when the operation usage is low the amount of use is low.
Silicon Mitus plans to supply customized chips according to the required current with the SM582x series. The company took account of different required current depending on the server capacity. The SM582x series currently supports 1.5A, 3.0A, and 4.5A.
Silicon Mitus claimed that it reduces wasted power by more than 5% higher efficiency compared to other products, and provides an option to set the chip according to the users’ required operation.
Dong-han Kim, Managing Director of Mobile Business Unit at Silicon Mitus, said, “We will develop power management chip products tailored to customer needs, not only in LPDDR, but also in SSD, NAND flash, and DDR markets in order to keep up with the rapidly expanding memory market demand.”
By Staff Reporter Yoon-seop Song sys@etnews.com