It Will Commercialize Processing at the End of Next Year
Samsung Electronics developed 10-nano FinFET processed S-RAM for the first time in the world. 10-nano S-RAMs that its competitors Intel and TSMC announced are still being processed at 14-nano and 16-nano. With development of 10-nano S-RAM, it will open up a door for a generation of Giga-Smartphone.
S-RAM, which is faster than D-RAM, is used for CPU’s cache memory. A fact that 10-nano S-RAM is developed indicates that preparation of equal system semiconductor processing’s mass-production is going very smoothly. If this trend continues, mobile application processor (AP) that has 10-nano technology will be mass-produced on full-scale in early 2017. It is expected that 10-nano AP will combine Gigabyte modem chips into one, which will make speed faster.
International Solid-State Circuits Conference (ISSCC) introduced an abstract of scientific paper, which was chosen to be published in 2016, that has this information on the 17th. ISSCC will be held in San Francisco from the 31st of January for 5 days in 2016.
10-nano FinFET processed S-RAM that Samsung Electronics is introducing at ISSCC has capacity of 128 Megabyte (MB) and cell area of 0.040 µm2. Compared to 14-nano S-RAM (0.064 µm2) that Samsung Electronics introduced in the past, its cell area is reduced by 37.5%. In its scientific paper, Samsung Electronics emphasized that it implemented large-scale cache memory, which is possible for fast operation, by most minimum area possible. It is expected that AP for Smartphone, which will have S-RAM, will be able to minimize Die’s area and improve its performance.
Announcement of development of 10-nano FinFET S-RAM implies that Samsung Electronics has not only surpassed Taiwan’s TSMC, but also Intel in level of progress in development of next-generation system semiconductor. It is essential to develop system semiconductor, which has CPU Core built in, in advance since it will have cache memory. Although Samsung Electronics and TSMC announced at ISSCC 2014, which was held in February of 2014, that it will develop 14-nano and 16-nano S-RAM respectively, Samsung Electronics was actually faster than TSMC in commercializing 16-nano S-RAM processing. Intel postponed its schedule for developing next-generation 10-nano system semiconductor from 2016 to 2017 due to increase of production cost according to advanced processing technologies. Samsung Electronics is targeting end of next year as a time period when it will commercialize 10-nano processing.
“Announcement of 10-nano S-RAM is done first and exclusively by Samsung Electronics in the world.” said an expert in this industry. “Samsung Electronics will be able to succeed in mass-producing 10-nano system semiconductors faster than Intel.”
Samsung Electronics also developed 14-nano flat-surface NAND-Flash, and this is also first ever in industries. Its competitors such as Toshiba, Micron and others have announced that after they finish developing 15 to 16-nanos, they will not develop any more flat-surface NAND-Flashes. It can be predicted that 14-nano NAND-Flash, which reduces area of Floating Gate by about 12.5% compared to 16-nano, will greatly contribute to Samsung Electronics in reducing production cost of NAND by reducing Silicon Die’s area.
It is predicted that Samsung Electronics’ Memory Business Department’s profit ratio will greatly improve due to development of 14-nano flat-surface NAND-Flash. Currently flat-surface NAND-Flash is being mass-produced at 16-nano. Until now industries were predicting that 15 and 16-nano will be last generation for flat-surface NAND-Flash and that it will rapidly change to layered 3D NAND-Flash afterwards. However as Samsung Electronics was able to develop 14-nano, flat-surface NAND-Flash’s life was able to extend furthermore.
14-nano NAND-Flash that Samsung Electronics introduced at ICCSS is a multi-level cell (MLC) product with capacity of 128 Gigabyte (Gb) and can save 2 bits per cell. If mass-production takes place in the future, it is expected to be supplied as embedded Multi-Media Card (eMMC) and Universal Flash Storage (UFS) interface that will be inside of Smartphones with high performance.
NAND-Flash differentiates 0 and 1 by either saving or taking out electron from Floating Gate and writes, erases, and reads data by doing so. Because area of Floating Gate reduces as circuit lines become finer, number of electrons that can be saved also reduces. It is known that number of electrons that 15 to 16-nano NAND-Flash can save into Floating Gate is under 10 and its number is even smaller for 14-nano. If there is not enough space for electrons that are able to be saved, then number of errors has to be low when data is read and written. For example, MLC method, which saves 2 bits (00, 01, 10, 11) per cell, differentiates 00, 01, 10, and 11 by whether or not there is no electron, little electrons, average amount of electrons and many electrons. It is difficult to avoid an error if there is no space in number of electrons that are saved. This is also reason why Samsung Electronics developed 14-nano NAND-Flash as MLC and not large-scale triple-level cell (TLC, able to save 3 bits, differentiates 8 levels) because lesser number of electrons means that there will be lesser errors. This structure limitation is reason why NAND-Flash industries are changing from flat-surface to layered-type. This is why Samsung Electronics’ 14-nano flat-surface NAND-Flash is receiving praises for overcoming limitation in technologies.
Staff Reporter Han, Jooyeop | firstname.lastname@example.org