Semiconductor Businesses Look to Lower Their Production Costs through AI Design

AI (Artificial Intelligence) technologies will be used for a process of designing high-integrated semiconductors. AI Technologies can reduce production cost by reducing repetitive process during design process of high-performance semiconductors that require tens of millions of dollars and increase efficiency in cooperation between designers. Global semiconductor businesses such as Samsung Electronics, Intel, and Qualcomm are looking to introduce ‘AI design’ system.
ANSYS, which is a company that specializes industrial design software (SW), made an announcement on the 21st that it applied Machine Learning algorithm called ‘KNN (K-Nearest-Neighbor’ to EM (Electro Migration) signoff tool that verifies if current flow is even for EDA (Electronic Design Automation) products.
KNN is a Machine Learning algorithm that is used widely to distribute certain data values automatically. Problems can occur whenever there is excessive amount of current in a particular area within a chip. It is a same logic as how roads are more easily damaged whenever there are overloaded vehicles. ANSYS’ EM signoff tool automatically checks whether there is appropriate amount of flow by using KNN algorithm. NVIDIA is currently using this tool for its design process of GPUs.
“Depending on level of learning, AIs can capture problems more accurately and faster without any help from people.” said Chief Technologist Norman Chang of ANSYS’ Semiconductor Business Department. “South Korean customers that have seen successful incidences of NVIDIA are showing high level of interests towards our technologies.”
Traditional powerhouses in EDA industries are continuously working to apply Machine Learning technologies to their design tools. Since 2013, Cadence has been adding Machine Learning function to its design verification tool called ‘Virtuoso’. Cadence explained that once this technology is developed, not only will it increase speed of design but it will also have abilities to make inferences and predictions.
Research teams from University of Illinois, University of North Carolina, and Georgia Institute of Technology established a research group called CAEML last year to look into ways to applying Machine Learning to EDA tools. Including NSF (National Science Foundation), CAEML is also receiving funds from Samsung Electronics, Intel, Qualcomm, Analog Device, NVIDIA, IBM, and HP.
Reason why global semiconductor businesses are showing much interests to AI design is due to production cost. Because number of chips that can be extracted from single sheet of waver goes up once processes become finer, production cost needs to be lowered. However, this kind of equation was broken once line width has become smaller than 20 nanometers. According to a market research company called International Business Strategy (IBS), production costs for 100 million gates of 20-nano FinFET process and 14/16-nano FinFET process are $1.42 and $1.62 respectively and they are 1.4 to 15.7% higher than production cost of 28-nano FinFET process ($1.4).
Rate of increase in production cost will be even higher for 10-nano, 7-nano, and 5-nano processes. Although level of technical difficulty can be a reason for this increase, complexity in design has huge impact on production cost. It is expected that economic feasibility for finer processes will become better once production cost drops from AI design.
Staff Reporter Han, Juyeop | powerusr@etnews.com