Increase in costs forsmaller micro-processes
3nm design costs 10x than that of 28nm
Overseas IP license another factor of burden
Concerns about oligopoly for companies with a high capital holding

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<Gate All-Around (GAA)-based Samsung Electronics 3nm Wafer>

The cost of designing advanced process semiconductors under 3nmestimated to KRW 720 billion. It is practically impossible if small to medium-sized fabless and startups do not have large sum of investment. There are concerns that only a small number of companies with large capital will be the main players in the next-generation semiconductor market, such as artificial intelligence (AI).
 
The cost of designing a semiconductor using a 3-nano process is up to $590 million (KRW 720 billion). The cost of designing with 5nm is $416 million and 7nm is $217 million which is a 41.8% and 171.8% increase, respectively. The 3-nano process requires 10x more funds compared to the current 28-nano process which costs about 40 million dollars.

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The IBS survey reflects the maximum cost of design, and the actual spending may have a difference. However, it is true that the cost increases significantly as the process is moving toward ultra-fine processing.
 
 An official from the semiconductor design house (Intellectual support) said, “The structure is setup in a way that the cost of entire process increases fromintellectual property (IP), electronic design automation (EDA), to prototype development. The trends for rising costs reaches from tens of billions to hundreds of billions KRW when designing with single-digit nano-processes.”
 
The significant increase in design cost is due to the increase in software (SW) and semiconductor IP costs, which account half of the initial design cost of semiconductors. The number of manpower required in semiconductor design increases significantly in the microprocessor progresses, in which semiconductor software license feerises accordingly. According to the industry, more than 100 people are needed to design a semiconductor of 5 nanometers. The number of software copy licenses that utilize EDA tools inevitably increases.An official from a small to medium-sized fabless said, "The 3 nano semiconductor IP is monopolized by some overseas companies; hence, the cost is non-negotiable.Small and medium-sized fabless companies have no choice but to pay the expensive IP costssince these companies do not have a leverage to negotiate efficiently.
 
Samsung Electronics, Qualcomm, Apple, Nvidia, and AMD are the only companies that are currently able to design 3-nano semiconductors.All of them are global semiconductor companies with a high capital holding, which allow them to negotiate efficiently with semiconductor software companies.
 
It is ‘unthinkable’ to enter the 3nm for small and medium-sized fabless and startups when they do not have any leverage to negotiate. There are only a handful of domestic semiconductor startups, such as Furiosa AI and Rebellions, thatdevelop semiconductor chips using the 5-14 nano process. Even though these companies succeeded in attracting tens of billions KRW in investment, they need to attract additional investment in order to design next-generation semiconductors.
 
The cost for developing prototype is also hold back small and medium-sized fabless companies, because the cost of the ‘multi-project wafer' (MPW), which draws the circuits on the wafer after semiconductor designing, is also expensive. The MPW (including IP cost) of the most advanced process currently ranges from KRW 2 to 4 billion.
 
It is practically impossible for small and medium-sized fabless to advance into neural network processing units (NPUs) and intelligent processing units (IPUs), which are so-called AI semiconductors, for these reasons. The AI semiconductors require using an ultra-fine process, but such companies are able to afford the the huge initial design cost.
 
An official from Innovation Center for System IC said, “There are only a handful of semiconductor fabless companies using under 14 nm in Korea due to cost issues. There is no other way than to attract a large sum of investment or to receive support for software costs of IP and EDA tools.”
 
<Advanced process semiconductor design cost>
 
Table provided by IBS

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 By Staff Reporter Dongjoon Kwon (djkwon@etnews.com)