The competition over ‘3D stacking technology’ to stack up semiconductor cells vertically rather than horizontally to improve NAND Flash performance has been kicked off. While Samsung Electronics, which has established a mass-production system, is leading the market, SK Hynix, Toshiba and Micron are accelerating the related technology development and mass-production.

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According to the semiconductor industry on the 15th, as NAND Flash 2D micro process has reached the limit due to signal interference between cells, key semiconductor makers are focusing on securing 3D technology to turn the cells formed on a flat surface into a vertical structure. The focus on competition in semiconductor industry is shifting from ‘micro processing’ to ‘vertical stacking ability.’

For a construction company to make more rooms within the same ground space, it is required to install a large number of partitions. However, as there are limitations, the construction company would increase rooms by building up more levels. Vertical semiconductor stacking is a similar concept.

In terms of 3D NAND, Samsung Electronics is most advanced. Last year, it completed 32-layer stacking, and thus commenced mass-production. In addition, this company is forecast to mass-produce a 48-layer semiconductor by the second half of this year. It plans to achieve up to 64-layer mass-production by the first half of next year. A step ahead of its competitors, Samsung Electronics has set out a strategy to secure unrivalled technological competitiveness in 3D field.

Samsung Electronics has set out a policy to utilize its plant in Xian, China as a 3D NAND production plant and decided to produce most of high-capacity solid state drives (SSD) in 3D NAND. The industry forecasts that Samsung Electronics will increase the percentage of 3D NAND from 15% this year to around 35% next year.

As for SK Hynix, it succeeded in developing a 24-layer NAND Flash last year, and thus supplied samples to some customers. This company is currently developing 36-layer and around 40-layer (estimated as 48-layer) semiconductors, which are equivalent to the 2nd and the 3rd generations respectively. SK Hynix plans to complete pilot production and mass-production verification within this year and then to start mass-production by selecting key products early next year.

Toshiba of Japan and Micron of the U.S. are forecast to commence mass-production as early as the end of this year. Both companies have secured 24-layer stacking technology, according to sources. The stacking layers for mass-production at the end of this year or early next year is forecast to be around 30 – 40 layers.

For 3D stacking, the core competitiveness is to be able to stack up many layers on the same area. This allows the manufacturer to secure a larger storage space (cells) while minimizing the area occupied in key devices. Assuming that the same process technology is used, 3D stacking improves writing speed by twice and writing frequency by up to ten times than 2D in theory. In addition, the degree of integration can be improved by more than twice and power consumption can be halved. Durability of 3D stacking is also far superior to that of 2D products.

“The technical hurdle point of memory semiconductor stacking technology has not yet been confirmed and it is being said that stacking design for more than 100 layers is sufficiently feasible,” said an industry insider. “However, in 3D, the degree of difficulty for etching and deposition increases considerably. Therefore, it is very important to secure advanced equipments.”